a. Field of the Invention
The present invention generally pertains to digital electronics and more particularly to electronic devices with multiple clock domains.
b. Description of the Background
Due to the nature of digital electronics almost all digital electronic designs utilize a clock to perform sampling of digital data. As the digital electronics become more complex the use of multiple clocks on the same device has become very common. The use of multiple clocks may create a system that has multiple clock domains. When data in one clock domain is needed in another clock domain, the data must be synchronized between the two domains to ensure that the timing differences between the two clock domains is accounted for properly.
A common device that has multiple clock domains is a transceiver. Typically there is a clock domain for the receiver and a clock domain for the transmitter. The transceiver may be either a serial or parallel communications transceiver. Multiple clock domains are not limited to just transceiver applications. Due to the necessity to periodically sample digital data, any digital electronic device may have multiple clocks and, thus, multiple clock domains. In addition to timing communication signals, the clock in the digital electronic device may be used to coordinate control signals. Control signals are the core of a smart electronic device and, hence, synchronizing multiple clock domains may be necessary on any digital electronic device.